高速多级时钟网布线  

High Speed Multilevel Staged Clock Routing\+*

作　　者：李芝燕[1] 严晓浪[2] 

机构地区：[1]浙江大学计算机系,杭州310027 [2]杭州电子工业学院CAD所,杭州310037

出　　处：《Journal of Semiconductors》2000年第3期290-297,共8页半导体学报（英文版）

基　　金：国家九五攻关项目!( 95-73 8-0 1 -0 8)

摘　　要：提出了一种新的加载缓冲器的时钟布线算法 .该算法根据时钟汇点的分布情况 ,在时钟布线之前对缓冲器进行预先布局 ,并将时钟树的拓扑生成及实体嵌入和层次式的缓冲器布局方法有机结合起来 ,使布线情况充分反映缓冲器对时钟网结构的影响 .实验证明 ,与将缓冲器插入和布局作为后处理步骤相比 ,缓冲器预先插入和布局在很大程度上避免了布线的盲目性 ,并能更加有效地实现各时钟子树的延迟和负载的平衡 .Clock routing is one of major steps in high performance driven layout design under deep sub micron technology. Buffered clock tree construction is a key factor for clock routing. A novel buffered clock routing algorithm is proposed. The strategy is to perform buffer insertion and placement according to clock sink distribution before clock net routing, and to optimize clock tree topology generation, detailed embedding following the buffer insertion process. The influence of the placed buffers on routing will be significantly reflected. The experimental results show that buffer pre\|placement will avoid blind routing in a great extent and achieve the balance of sub\|tree delay and load capacitance efficiently.

关 键 词：时钟布线 版图设计 VLSI 集成电路 

分 类 号：TN405.97[电子电信—微电子学与固体电子学] TN402