A 5.3-GHz 32-bit accumulator designed for direct digital frequency synthesizer  

作　　者：CHENJianWu WUDanYU ZHOULei WUJin JINZhi LIUXinYu 

机构地区：[1]Institute ofMicroelectronics, Chinese Academy ofScienees, Beijing 100029, China [2]Key Laboratory of Microelectronics Devices ＆ Integrated Technology, Institute of Microelectronics, Chinese Academy of S~＇iences, Betjing 100029, China

出　　处：《Chinese Science Bulletin》2012年第19期2480-2487,共8页

基　　金：supported by the National Basic Research Program of China (2010CB327505)

摘　　要：A 32-bit pipeline accumulator with carry ripple topology is implemented for direct digital frequency synthesizer.To increase the throughout while hold down the area and power consumption,a method to reduce the number of the pre-skewing registers is proposed.The number is reduced to 29% of a conventional pipeline accumulator.The propagation delay versus bias current of the adder circuit with different size transistors is investigated.We analyze the delay by employing the open circuit time constant method.Compared to the simulation results,the maximum error is less than 8%.A method to optimum the design of the adder based on the propagation delay is discussed.The clock traces for the 32-bit adder are heavily loaded,as there are 40 registers being connected to them.Moreover,the differential clock traces,which are much longer than the critical length,should be treated as transmission lines.Thus a clock distribution method and a termination scheme are proposed to get high quality and low skew clock signals.A multiple-type termination scheme is proposed to match the transmission line impedance.The 32-bit accumulator was measured to work functionally at 5.3 GHz.A 32-bit pipeline accumulator with carry ripple topology is implemented for direct digital frequency synthesizer. To increase the throughout while hold down the area and power consumption, a method to reduce the number of the pre-skewing registers is pro- posed. The number is reduced to 29% of a conventional pipeline accumulator. The propagation delay versus bias current of the adder circuit with different size transistors is investigated. We analyze the delay by employing the open circuit time constant method. Compared to the simulation results, the maximum error is less than ＋_8%. A method to optimum the design of the adder based on the propagation delay is discussed. The clock traces for the 32-bit adder are heavily loaded, as there are 40 registers be- ing connected to them. Moreover, the differential clock traces, which are much longer than the critical length, should be treated as transmission lines. Thus a clock distribution method and a termination scheme are proposed to get high quality and low skew clock signals. A multiple n-type termination scheme is proposed to match the transmission line impedance. The 32-bit accumula- tor was measured to work functionally at 5.3 GHz.

关 键 词：直接数字频率合成器 累加器 32位 设计 传播延迟 差分时钟 加法器 偏置电流 

分 类 号：TN741[电子电信—电路与系统] TN74