65nm工艺下面积功耗优化的BCH电路设计  

Design and Optimization of Area and Power BCH Circuit in 65nm Process

作　　者：莫海锋[1,2] 张耀辉[1] 

机构地区：[1]中国科学院苏州纳米技术与纳米仿生研究所,江苏苏州215123 [2]中国科学院研究生院,北京100049

出　　处：《半导体技术》2012年第7期508-512,共5页Semiconductor Technology

摘　　要：在65 nm工艺下实现了最大纠正84 bit错误的带循环冗余码(CRC)校验保护功能的BCH(32767,16416)纠错电路,纠错能力可配置。该设计采用频率比为1∶4的两种工作时钟,最高工作频率为100 MHz和400 MHz。两种工作频率的合理组合降低译码运算的延迟,提高固态硬盘读写数据的性能,同时提供了分时复用的可能。通过复用伴随式计算、关键方程系数求解(iBM算法)和钱搜索过程中的有限域乘法运算单元优化芯片面积。通过调整钱搜索的起始位置,实现编码和伴随式计算的求余电路复用,实现面积和功耗的优化,最终芯片面积节省了27%,功耗降低了26%。Bose Chandhari Hocquenghem （BCH） （32767, 16416） with the maximum 84 bit errors correction ability and cyclic redundancy codes （CRC） function was implemented in 65 nm process. The configurable continuum correction ability was supported. The circuit could work at 100 MHz and 400 MHz clock frequency to reduce the decoding latency to improve solid state drive （SSD） performance. It＇s possible to use the same finite field multipliers at different time. The multiplier of syndrome calculation, iBM algorithm, and Chien search in finite field were shared to save area. The liner feedback shift register of eneoder was shared with syndrome calculation by moving the Chien search start point. More than 27% of the chip area and 26% of power were saved.

关 键 词：BCH码 面积优化 有限域乘法器 iBM算法 钱搜索 

分 类 号：TN492[电子电信—微电子学与固体电子学]