一种高性能鉴频鉴相器的设计  

Design of Phase Frequency Detector with High Performance

作　　者：吕荫学[1] 刘梦新[1] 罗家俊[1] 叶甜春[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《半导体技术》2012年第7期538-543,共6页Semiconductor Technology

摘　　要：分析了电荷泵型锁相环中鉴相器和电荷泵的非理想因素及优化设计方法。基于台积电公司(TSMC)0.35μm 2层多晶硅4层金属(2P4M)CMOS工艺,设计了一种低杂散的鉴频鉴相器结构,该结构通过"自举"的方法,用单位增益放大器使充放电前后开关管各节点处的电压保持不变,从而消除了电荷共享的影响,减小了鉴相器的输出杂散。仿真结果表明相比于传统鉴相器结构,该鉴频鉴相器有效抑制了电荷共享问题,电荷泵开关管开启时的充放电电流尖峰大大减小了,鉴相前后的电压波动小于200μV,脉冲尖峰仅为3.07 mV,有效降低了鉴频鉴相器的输出杂散。The nonideal effects and the optimized design method of the phase frequency detector and charge pump in the phase lock loop （PLL） systems were proposed. Based on TSMC 0.35 μm 2P4M CMOS process, a new phase frequency detector （PFD） was proposed. The PFD used a ＂bootstrapping＂ structure, which is contained of two unit gain amplifiers. To make the voltage of each node of the PFD circuit remains the same before and after charging, so as to suppress the influence of charge sharing phenomenon, thereby reducing the output of the phase spurious. Simulation results of the circuit with cadence spectre show that the new PFD has better overall performance compared with typical PFD. The charge sharing problem is effectively restrained. After phase detected, the voltage fluctuation is less than 200 trV and the pulse peak is only 3.07 mV, the spurs of the PFD output is effectively reduced.

关 键 词：鉴频鉴相器 锁相环 电荷泵 抖动 非理想效应 

分 类 号：TN763.3[电子电信—电路与系统]