一种表达式粒度可重构阵列的VLSI架构及应用  

A VLSI Architecture and Application for Expression-Grained Reconfigurable Array Accelerator

作　　者：王浩[1] 何卫锋[1] 

机构地区：[1]上海交通大学微电子学院,上海200240

出　　处：《微电子学与计算机》2012年第7期8-12,共5页Microelectronics & Computer

基　　金：国家"八六三"计划项目(2009AA011705)

摘　　要：提出一种表达式粒度可重构阵列的VLSI架构,主要面向具有高计算密集度和高数据并行度的应用,如视频编解码.每个处理单元内部包含4个异构数据通路单元,能够映射一个运算表达式,处理单元之间采用三层互联结构.阵列内部包括128位带宽的数据存储模块,具有数据乱序分发和拼接能力,核心计算循环能够映射到可重构阵列上执行.对包含16个处理单元的架构原型进行建模,采用TSMC 90nm工艺综合,工作频率达100MHz,芯片面积为1.38mm2.对2D-DCT算法进行性能比较,结果显示该架构具有更好的计算资源利用率和面积效率.This paper presents a VLSI architecture of an expression-grained reconfigurable array,which is mainly used for applications with high computation-intensity and data-parallelism,like video decoding.Each processing element contains 4 heterogeneous data-path units and an expression can be mapped on it.There is a three hierarchy levels interconnect structure between PEs.The array contains 128-bit data memories and has the capability of data distributing and joining.The kernel computing loop can be mapped on the array.We developed an architecture prototype with 16 PEs and synthesized it using TSMC 90nm process library.The frequency is about 100MHz and the core area is about 1.38mm2.The algorithm of 2D-DCT is simulated and compared with other architectures,and the result shows that our architecture has better computing and area efficiency.

关 键 词：可重构阵列 表达式粒度 异构单元 算法映射 核心计算循环 

分 类 号：TN47[电子电信—微电子学与固体电子学]