一种基于JTAG接口的片上调试与性能分析方法  

A Method of On-Chip-Debugger and Performance Analysis Based on JTAG Interface

作　　者：高瑛珂[1,2] 王琪[1,2] 李泉泉[1,2] 张铁军[2] 侯朝焕[2] 

机构地区：[1]中国科学院研究生院,北京100190 [2]中国科学院声学研究所,北京100190

出　　处：《微电子学与计算机》2012年第7期68-71,共4页Microelectronics & Computer

基　　金：国家"核高基"项目(2009zx01034-001-002-005)

摘　　要：介绍了一种复用JTAG标准接口来实现处理器片上调试和性能分析的方法.以SuperV DSP处理器为研究对象,通过设计调试和性能分析模块以及相应指令,实现了运行控制,断点设置等调试功能以及统计执行周期数,Cache缺失率等性能分析数据的功能,极大地方便软件开发和应用程序优化,同时对处理器性能和功耗影响甚微.This paper introduces a kind of method to achieve processor on-chip debugging and performance analysis by reusing JTAG interface.With SuperV DSP as the research prototype,in the scheme both debugger and performance analysis modules are designed and the corresponding instructions are extended to provide the following capabilities for on-chip debugging and performance analysis： run-control,breakpoint setting,the execution cycle numbers and cache missing rate counting.Software development and application optimization are greatly facilitated,with little effect on the processor performance and power consumption.

关 键 词：JTAG 片上调试 性能分析 复用 SuperV处理器 

分 类 号：TN7[电子电信—电路与系统]