2-1-1级联连续时间型ΣΔ调制器系统设计  

System Design of 2-1-1 Cascaded Continuous-Time ΣΔ Modulator

作　　者：沈琪[1] 王伟印[1] 顾晓峰[1] 赵琳娜[1] 于宗光[2] 

机构地区：[1]轻工过程先进控制教育部重点实验室,江南大学电子工程系,江苏无锡214122 [2]中国电子科技集团公司第58研究所,江苏无锡214035

出　　处：《微电子学与计算机》2012年第7期107-111,共5页Microelectronics & Computer

基　　金：国家自然科学基金(11074280);中央高校基本科研业务费专项资金(JUSRP20914,JUDCF10031);江苏省普通高校研究生创新计划(CXLX11_0486)

摘　　要：高阶连续时间型ΣΔ调制器提供了一种有效的获得高分辨率、低功耗模数转换器的方法.提出了一种新型的2-1-1级联的连续时间型ΣΔ调制器结构.采用冲激不变法将离散时间型ΣΔ调制器变换为连续时间型ΣΔ调制器,利用Simulink对该调制器进行系统级建模和仿真,峰值信噪比达到105dB.分析了电路的非理想因素对调制器行为的影响,以获得90dB信噪比为目标确定了电路子模块指标.仿真结果表明,该结构能有效降低系统功耗,并验证了电路的可行性.High order continuous-time ΣΔ modulator provides an effective way to realize analog-digital converters of high resolution and low power consumption.A novel 2-1-1 cascaded continuous-time ΣΔ modulator has been proposed by transforming the discrete-time ΣΔ modulator to the continuous-time one using the impulse-invariant transformation.The continuous-time ΣΔ modulator is modeled and simulated using Simulink,obtaining a peak signal-to-noise ratio of 105 dB.The effects of circuit non-ideal factors on the modulator performance are then analyzed.The detailed indices of circuit sub-modules are determined by setting a signal-to-noise ratio of 90 dB as the design aim.Simulation results indicate that this modulator architecture can lower the system power consumption effectively,and the feasibility of circuits is successfully verified.

关 键 词：连续时间 ΣΔ调制器 级联结构 非理想因素 

分 类 号：TN4[电子电信—微电子学与固体电子学]