基于ADF4002的低相噪取样本振设计  

Design of low phase noise sampling LO based on ADF4002

作　　者：李柏林[1] 陈丽[1] 郝绍杰[1] 

机构地区：[1]中国电子科技集团公司第四十一研究所,青岛266555

出　　处：《国外电子测量技术》2012年第6期51-54,共4页Foreign Electronic Measurement Technology

摘　　要：本文设计并实现了一种微波锁相环中取样器的本振电路,取样本振以频率合成芯片ADF4002为鉴相器,反馈通道采用内插混频器的结构,避免了单环通过简单倍频产生的相位噪声恶化。详细阐述了取样本振电路的实现方案和工作原理,并使用仿真软件对环路滤波器进行设计。通过实验测试,输出频率为214.815MHz时锁相环的相位噪声为:-137dBc/Hz@10kHz、-140dBc/Hz@100kHz,最大输出频率间隔1MHz,满足了取样本振的低相位噪声和高频率分辨率的要求。A local oscillator （LO） circuit of sampling phase detector for microwave PLL is designed and realized in this pa-per. The frequency synthesizer chip ADF4002 is used as phase detector of the sampling LO and mixer is introduced infeedback path to avoid deterioration of phase noise due to frequency multiplication. The detailed implementation and working principle of the PLL is given in the paper,and simulation software is used to design the loop filter. Experiments result shows that the phase noise is -137dBc/Hz@10kHz,-140dBc/Hz@100kHz at output frequency of 214. 815MHz and the maximum output frequency space is 1MHz, which meets the low phase noise and high frequency resolution of sampling LO.

关 键 词：取样本振 相位噪声 锁相环 混频 

分 类 号：TN742[电子电信—电路与系统]