A high-speed mixed-signal down-scaling circuit for DAB tuners  

作　　者：唐路 王志功 玄甲辉 杨旸 徐建 徐勇 

机构地区：[1]Institute of RF-&OE-ICs,Southeast University [2]Institute of Sciences,PLA University of Science and Technology

出　　处：《Journal of Semiconductors》2012年第7期108-112,共5页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(No.61106024);the Specialized Research Fund for the Doctoral Program of Higher Education,China(No.20090092120012);the Science and Technology Program of Southeast University(No. KJ2010402)

摘　　要：A high-speed mixed-signal down-scaling circuit with low power consumption and low phase noise for use in digital audio broadcasting tuners has been realized and characterized. Some new circuit techniques are adopted to improve its performance. A dual-modulus prescaler （DMP） with low phase noise is realized with a kind of improved source-coupled logic （SCL） D-flip-flop （DFF） in the synchronous divider and a kind of improved complementary metal oxide semiconductor master-slave （CMOS MS）-DFF in the asynchronous divider. A new more accurate wire-load model is used to realize the pulse-swallow counter （PS counter）. Fabricated in a 0.18-#m CMOS process, the total chip size is 0.6× 0.2 mm2. The DMP in the proposed down-scaling circuit exhibits a low phase noise of-118.2 dBc/Hz at 10 kHz off the carrier frequency. At a supply voltage of 1.8 V, the power consumption of the down-scaling circuit＇s core part is only 2.7 mW.A high-speed mixed-signal down-scaling circuit with low power consumption and low phase noise for use in digital audio broadcasting tuners has been realized and characterized. Some new circuit techniques are adopted to improve its performance. A dual-modulus prescaler （DMP） with low phase noise is realized with a kind of improved source-coupled logic （SCL） D-flip-flop （DFF） in the synchronous divider and a kind of improved complementary metal oxide semiconductor master-slave （CMOS MS）-DFF in the asynchronous divider. A new more accurate wire-load model is used to realize the pulse-swallow counter （PS counter）. Fabricated in a 0.18-#m CMOS process, the total chip size is 0.6× 0.2 mm2. The DMP in the proposed down-scaling circuit exhibits a low phase noise of-118.2 dBc/Hz at 10 kHz off the carrier frequency. At a supply voltage of 1.8 V, the power consumption of the down-scaling circuit＇s core part is only 2.7 mW.

关 键 词：PLL DMP down-scaling circuit CMOS 

分 类 号：TN934.3[电子电信—信号与信息处理]