E1/LAN反向复用技术的FPGA实现  

FPGA Implementation of E1/LAN Inverse Multiplexing Technology

作　　者：宣二勇[1] 常立新 王俊芳[1] 

机构地区：[1]中国电子科技集团公司第五十四研究所,河北石家庄050081 [2]总参信息化部驻石家庄地区军代室,河北石家庄050081

出　　处：《无线电工程》2012年第7期7-9,43,共4页Radio Engineering

摘　　要：针对以太网通过E1链路接入同步数字系列(SDH)的应用需求,利用现场可编程门阵列(FPGA)完成了将以太网数据包反向复用到多路E1链路上传输的实现方法。介绍了系统总体设计和功能划分,重点描述了各组成模块的设计方法,解决了差分时延补偿和链路动态调整2项关键技术。相对于利用专用集成芯片完成的实现方法,该方法具有设备体积小、功耗低、可扩展性强和可靠性高等优点。对实现的设备进行了测试,测试结果满足功能和性能要求,具有良好的应用前景。In order to meet application requirement that Ethernet connects to SDH network throuigh E1 link, a design method which inverses multiplex Ethernet packets on several E1 links is proposed by using FPGA. Firstly,the overall design and function division of the system are introduced, and then the design method of main components is elaborated. Two critical technologies such as differ- ential delay compensation and link dynamic adjustment are resolved in the paper. Comparing to the designs that are fulfilled by using ASIC,this design has such advantages as small volume,low power, strong expansibility and high reliability. Finally,the device based on the method is tested, the result shows that the device meets the function and performance requirements and has broad application prospect.

关 键 词：现场可编程门阵列 反向复用 差分时延补偿 链路动态调整 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]