基于FPGA的时序脉冲发生器设计  

The Design of Timing Pulse Generator Based on FPGA

作　　者：颜丽[1] 王伟[2] 

机构地区：[1]萍乡高等专科学校,江西萍乡337000 [2]九江职业技术学院,江西九江332007

出　　处：《九江职业技术学院学报》2012年第2期17-19,6,共4页Journal of Jiujiang Vocational and Technical College

摘　　要：本文在实现时序脉冲发生器的设计中,利用现场可编程门阵列改变了传统设计方法,进一步方便了对硬件的修改与调试。通过综合分析采用标准二进制计数器的时序脉冲发生器的工作原理,针对采用标准二进制计数器的时序脉冲发生器所产生的"竞争-冒险"现象提出改进方法,即采用约翰逊计数器作为时序脉冲发生器的计数器,并利用函数化简的方法进一步简化电路,从而对"竞争-冒险"干扰现象提出了一种合理的消除方法。In the design of realization to the timing pulse generator, field programmable gate array was used to change the traditional methods of design, and made modifying and debugging hardware more facilitate. The working principle of a standard binary counter formed timing pulse generator was analyzed comprehensively, the improving method was take to eliminate the predominance of ＂competition - adventure＂ produce by the standard binary counter formed timing pulse generator, Johnson counter was used as the counter of a timing pulse generator counter, and used of the SR function method further simplify the circuit, thereby timing pulse interference presents a method to eliminate reasonable. The reasonable method to eliminate the ＂competition - adventure＂interference of timing pulse was taken.

关 键 词：可编程逻辑门阵列 时序脉冲发生器 约翰逊计数器 竞争-冒险 

分 类 号：TP33[自动化与计算机技术—计算机系统结构]