基带信号插值滤波器的设计及其FPGA实现  

The Design of Baseband Signal Interpolation Filter and its Implementation on FPGA

作　　者：张文帅[1] 唐博[1] 秦开字[1] 

机构地区：[1]电子科技大学空天科学技术研究院,成都611731

出　　处：《自动化信息》2012年第7期35-37,22,共4页Automation Information

摘　　要：本文主要介绍了由内插滤波器特性较好的级联积分梳状滤波器CIC和补偿滤波器FIR级联的插值滤波器的结构。直接在FPGA中调用滤波器的IP核，采用多级级联的方式，这种结构的插值滤波器能有效地实现该设计提高基带信号采样率的要求。通过XILINX时序仿真验证了该结构的高效性和正确性，在实际矢量信号发生器研制中可推广应用。This article mainly introduces the structure of the interpolation filter cascaded by the CIC filter and compensating fil- ter FIR, the former has the better characteristics of interpolating filter. By directly calling IP core of the filter in the FPGA and using the mode of multilevel cascading, the interpolation filter with this structure is able to effectively achieve the requirements of enhanc- ing the sampling rate of baseband signal in the design. The high efficiency and correctness of the structure are verified by means of Xilinx timing simulation, the design can be widely applied to the development of practical vector signal generator.

关 键 词：基带信号 CIC插值滤波器 FIR补偿滤波器 FPGA 

分 类 号：TN911.3[电子电信—通信与信息系统]