Incremental Min-Period Retiming Algorithm for FPGA Synthesis Based on Influence of Fan-Outs  

作　　者：郝亚男 杨海钢 崔秀海 谭宜涛 路宝珠 

机构地区：[1]Institute of Electronics,Chinese Academy of Sciences [2]Graduate University of Chinese Academy of Sciences

出　　处：《Transactions of Tianjin University》2012年第4期259-265,共7页天津大学学报（英文版）

基　　金：Supported by Major National Scientific Research Plan (No. 2011CB933202)

摘　　要：An improved linear-time retiming algorithm is proposed to incrementally optimize the clock period, espe cially considering the influence of the in-out degree of the critical combinational elements. Firslly, the critical elements are selected from all the critical combinational elements to retime. Secondly, for the nodes that cannot be performed with such retiming, register sharing is implemented while the path delay is kept unchanged. The incremental algorithm can be applied with the technology mapping to minimize the critical path delay and obtain fewer registers in the re- timed circuit with the near-optimal clock period. Compared with Singh＇s incremental algorithm, experiments show that the proposed algorithm can reduce the flip-flop count by 11% and look-up table （LUT） count by 5% while improv- ing the minimum clock period by 6%. The runtime is also reduced by 9% of the design flow.An improved linear-time retiming algorithm is proposed to incrementally optimize the clock period,especially considering the influence of the in-out degree of the critical combinational elements.Firstly,the critical elements are selected from all the critical combinational elements to retime.Secondly,for the nodes that cannot be performed with such retiming,register sharing is implemented while the path delay is kept unchanged.The incremental algorithm can be applied with the technology mapping to minimize the critical path delay and obtain fewer registers in the retimed circuit with the near-optimal clock period.Compared with Singh's incremental algorithm,experiments show that the proposed algorithm can reduce the flip-flop count by 11% and look-up table(LUT) count by 5% while improving the minimum clock period by 6%.The runtime is also reduced by 9% of the design flow.

关 键 词：linear-time retiming sequential optimization sharing register field programmable gate array （FPGA） 

分 类 号：TN791[电子电信—电路与系统]