一种高效的三维DWT VLSI结构设计方法  

VLSI architecture design with highly efficient for 3D DWT

作　　者：高涛[1] 白璘[1] 

机构地区：[1]长安大学信息工程学院,陕西西安710064

出　　处：《电子设计工程》2012年第14期120-122,共3页Electronic Design Engineering

基　　金：中央高校基本科研业务费专项资金(CHD2011JC067;CHD2011JC170)

摘　　要：文中通过深入研究三维离散小波变换(3D DWT)核心算法并根据序列图像编码的特点,设计并实现了一种适合硬件实现的高效的三维小波变换VLSI结构。编写了相应verilog模型,并进行了仿真和逻辑综合。仿真结果表明行列滤波并行处理并采用流水线设计方法,加快了运算速度,有效降低了片内存储容量。A VLSI architecture with highly efficient for three dimensional discrete wavelet transform（3D DWT） is presented by studying 3D DWT core algorithm in deepness and according to image characteristic.The hardware structure of 3D wavelet video coder is designed,and the verilog modules are programmed,simulated and synthesized.The result show that processing a few datum with row filter operations that are paralleling with column filter operations,the on-chip memory capacity is progressively reduced.Furthermore,the architecture of the row filter and column filter and a pipelined method adopt that can speed up the transforms and improves the hardware utilization.

关 键 词：三维小波变换 VLSI 提升算法 verilog模型 

分 类 号：TN406[电子电信—微电子学与固体电子学] TP391.41[自动化与计算机技术—计算机应用技术]