基于FPGA的高速DUC设计与高效实现  

Design and Efficient Realization of High Speed DUC Based on FPGA

作　　者：张海峰[1] 赵爱玲[1] 

机构地区：[1]安阳工学院机械工程学院,河南安阳455000

出　　处：《电讯技术》2012年第7期1112-1115,共4页Telecommunication Engineering

基　　金：河南省高等学校青年骨干教师基金项目(2011GGJS-212)~~

摘　　要：提出了一种基于FPGA实现高速数字上变频(DUC)的方法。该方法采用一种新的多相内插滤波器的高效实现结构,利用多相内插滤波器中各分支滤波器间系数的特点,使多相内插滤波器消耗的乘法器数量减少一半;并采用一种并行结构的数控振荡器(NCO),可产生高数据率的上变频本振信号。利用该方法为某雷达中频回波模拟器设计了DUC模块,其输出数字中频信号的数据率可达1.2 Gsample/s,只消耗了少量资源,满足项目需求。This paper proposes an access to the realization of high data rate digital up converter（DUC） based on FPGA. This method adopts a novel implementation structure of poly - phase interpolation filter and makes use of the characteristic of branch between filter coefficients to reduce the consumption of multiplier by half. Besides, the adoption of parallel processing Numerically- controlled Oscillator（NCO） can generate high data rate vibra- tion signal. By following these methods, a DUC module is designed for a certain radar IF echo simulator, which can generate digital IF signal with data rate up to 1.2 Gsample/s. Few resources are consumed and the program needs are satisfied.

关 键 词：雷达回波模拟器 高速DUC 高效多相内插滤波器 并行NCO 数字中频信号 

分 类 号：TN955[电子电信—信号与信息处理]