像素碲锌镉探测器低噪声读出芯片设计与测试  被引量:2

Design and test results of a low-noise readout ASIC for pixelated CdZnTe detectors

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作  者:罗杰[1] 邓智[1] 刘以农[1] 王光祺 李红日 

机构地区:[1]清华大学工程物理系,粒子技术与辐射成像教育部重点实验室,北京100084 [2]北京滨松光子技术有限公司,北京100070

出  处:《清华大学学报(自然科学版)》2012年第7期917-921,共5页Journal of Tsinghua University(Science and Technology)

基  金:国家自然科学基金资助项目(10735060)

摘  要:为了解决像素碲锌镉探测器的高密度和低噪声读出问题,设计了一款8通道的低噪声前端读出芯片。每个通道由两级电荷灵敏前放、4阶半Gauss成形电路和输出驱动放大器组成。芯片采用了0.35μm CMOS工艺完成了流片测试,单通道的电荷增益为65~260mV/fC,成形时间调节范围为1~4μs,测得的最好等效噪声电荷为200e。连接碲锌镉探测器后测得241 Am和57 Co全能峰的能量分辨率分别为9.6%和5.9%。初步测试结果表明:芯片的各项功能都正常,噪声的实测结果与仿真结果比较吻合,但探测器的漏电流以及输入端寄生电容使得其电子学噪声显著增加。An 8 channel low noise front-end readout chip was designed to provide readouts from a highly pixelated cadmium zinc telluride (CdZnTe) detector. Each channel consists of a two-stage charge sensitive amplifier, a 4 th order semi-Gaussian shaper and an output buffer. The chip was fabricated in the 0.35 μm CMOS process. The channel gain is 65- 260 mV/fC and the shaping time is 1 - 4 Vs. The device has a minimum equivalent noise charge of 200e. The circuit and the CdZnTe detector gave an energy resolution of 9.6% for ^241Am photopeaksand 5.9% for 57Co. The results show that this chip functions well with the measured noise in agreement with simulation results. The detector leakage current and the parasitic capacitance at the input significantly increase the electronic noise.

关 键 词:碲锌镉 室温半导体探测器 低噪声 专用集成电路(ASIC) 

分 类 号:O5[理学—物理]

 

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