基于区域重组的异构FPGA工艺映射算法  

Technology Mapping for Heterogeneous FPGA Based on Regional Regrouping

作　　者：路宝珠[1,2] 杨海钢[1] 郝亚男[1,2] 张茉莉[1,2] 崔秀海[1] 

机构地区：[1]中国科学院电子学研究所可编程芯片与系统研究室,北京100190 [2]中国科学院研究生院,北京100049

出　　处：《计算机辅助设计与图形学学报》2012年第8期1027-1037,共11页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家"九七三"重点基础研究发展计划项目(2011CB 933202);国家自然科学基金(61106033)

摘　　要：传统异构FPGA工艺映射算法一般不打破实现专用功能和查找表功能的子网表之间的层次边界,因而缩小了映射的优化空间.为此提出一种利用区域重组打破单元间层次边界的异构FPGA工艺映射算法.首先利用贪心策略实现FPGA多单元的映射,即优先使用性能好的专用功能单元;然后利用标记锥实现子网表之间的区域重组,打破专用功能单元和查找表之间的层次边界,减小了映射结果的面积和延迟开销.实验结果表明,与公认的ABC中的工艺映射算法相比,该算法能平均减少逻辑单元面积12.2%,减少电路关键路径延时2.5%.Traditional technology mapping algorithms don＇t break hierarchical boundary between specific-purpose blocks and LUTs for heterogeneous FPGA, thereby the solution space of mapping could be decreased to some extent. This paper proposes an efficient technology mapping algorithm by utilizing a regional regrouping approach to break hierarchical boundary between those heterogeneous blocks. It first adopts greedy heuristics for general mapping through giving priority to specific-purpose blocks with good performance, and then takes advantage of self-defined signed-cones to implement regional regroup among sub-netlists. Benefiting from regrouping strategy, it not only breaks the hierarchical boundary between specific-purpose blocks and LUT, and also reduces the cost of area and delay. Experimental results show this algorithm can reduce area of logic blocks by 12.2% and decrease circuit delay by 2.5% on average, compared to acknowledged Berkeley ABC mapping algorithm.

关 键 词：FPGA 异构FPGA工艺映射 专用功能单元 区域重组 标记锥 

分 类 号：TN402[电子电信—微电子学与固体电子学]