新型高频高线性CMOS跨导线性电流模乘/除法器设计  

Novel High-frequency High-linear CMOS Translinear Current-mode Multiplier/Divider

作　　者：解鸿国[1] 宋树祥[1] 

机构地区：[1]广西师范大学电子工程学院,广西桂林541004

出　　处：《广西师范大学学报（自然科学版）》2012年第2期12-16,共5页Journal of Guangxi Normal University:Natural Science Edition

基　　金：国家自然科学基金资助项目(61061006)

摘　　要：针对传统CMOS电流乘除法器存在线性度不高、工作频率低等缺点,提出一种以平方根电路、平方/除法器电路为核心的基于MOS管跨导线性原理的新型高频高线性CMOS电流模乘/除法器。在TSMC0.35μm CMOS集成工艺下进行HSPICE仿真测试表明:该电路在3V电源电压下,-3dB带宽可达到35.1MHz,电源静态功耗为202.68μW,输出电流为0～25.1μA,非线性误差为0.85%,总谐波失真为0.14%。本文提出的乘除法器电路与Tanno、Lopez等提出的基于跨导线性原理的乘除法器电路相比,优点在于-3dB带宽提高了,功耗降低了,电源电压降低了,线性度提高了,精度提高了,并且采用了相对更先进的0.35μmCMOS工艺,可缩小芯片面积,节约成本。In view of the shortcoming of conventional CMOS current multiplier/divider in low linearity and low frequency ,a novel CMOS current mode multiplier/divider based on MOS Translinear rule,with square-root and squarer/divider circuit for core circuit, is proposed. HSPICE simulation test using TSMC＇s 0.35μm CMOS process model show a -3 dB bandwidth of 35. 1 MHz for the circuit,working at a supply voltage of 3 V,and its static power consumption is 202.68 #W,output current range 0-25.1 9A,nonlinear error 0.85% and total harmonic distortion 0. 14 %. Compared with the multipliers/dividers designed by Tanno,Lopez,et al. ,the proposed multiplier/divider circuit has many advantages,using -3 dB bandwidth ,reduced power consumption,reduced power supply voltage,improved linearity,raised accuracy,and a relatively more advanced 0. 35 μm CMOS technology,and saving chip area.

关 键 词：平方根电路 平方/除法器电路 乘法器/除法器 跨导线性原理 

分 类 号：TN432[电子电信—微电子学与固体电子学]