片上网络中低延时可扩展的路由器结构设计  

Structure design of low-latency extensible router in network on chip

作　　者：张媛媛[1] 孙光[1] 苏厉[1] 金德鹏[1] 曾烈光[1] 

机构地区：[1]清华大学电子工程系微波与数字通信技术国家重点实验室,北京100084

出　　处：《传感器与微系统》2012年第8期134-136,共3页Transducer and Microsystem Technologies

基　　金：国家自然科学基金资助项目(90607009);国家自然科学基金创新研究群体项目(61021001);国家"863"计划资助项目(2008AA01Z107)

摘　　要：为了满足片上网络中路由器能同时支持多个IP核的要求,并同时具有较好的延时性能,设计了一种分布式路由和仲裁的路由器结构。其中的仲裁模块根据当前路由器各输入端口的请求状态和下一路由器相应输入端口缓冲器的状态进行仲裁,此仲裁方法提高了数据包传输的成功率,从而降低了传输延时,使路由器具有良好的延时性能,同时仿真结果表明:该路由器在面积开销方面具有良好的可扩展性。To satisfy the requirement that the router in network on chip can support multiple IP cores, and its latency performance is good, a router with a distributed routing and arbitrating structure is designed. Its arbitration module arbitrates on the request state of the current router and the state of the input buffer in the next router,this arbitration method improves the success rate of the packet transmission, so it decreases the transmission latency and improves latency performance of the router, meanwhile the simulation results indicate the router has good expansibility in area overhead.

关 键 词：片上网络 路由器 低延时 可扩展 

分 类 号：TN492[电子电信—微电子学与固体电子学]