基于ARM Cortex-M3核的SoC架构设计及性能分析  

Design and performance analysis of SoC architecture based on ARM Cortex-M3

作　　者：陶友龙[1] 赵安璞[1] 陈海波[1] 

机构地区：[1]东南大学国家ASIC系统工程技术研究中心(无锡),江苏无锡214135

出　　处：《电子技术应用》2012年第8期53-55,共3页Application of Electronic Technique

摘　　要：主要研究了基于ARM Cortex-M3核的SoC设计方法及不同架构对芯片整体性能的影响。首先从Cortex-M3的结构特点尤其是总线结构特点出发,分析了基于该核的SoC架构设计的要点。然后通过EEMBC的CoreMark程序,对实际流片的一款Cortex-M3核芯片进行了性能测试,并与STM32F103 MCU的测试结果进行了对比,通过实例说明了不同芯片架构对性能的影响。最后,对影响SoC芯片性能的因素,包括芯片架构、存储器速度、工艺、主频等进行了分析和总结。The method of how to design SoC with ARM Cortex-M3 core is carefully studied, and the relationship between chip architecture and performance is also analyzed. Firstly, the essentials of SoC design with Cortex-M3 are presented based on the core＇s structural features, especially the bus structure feature. Then, with the help of CoreMark program from EEMBC, the performance of a chip with Cortex-M3 core is tested after tape-out, and also compared with the test results of STM32F103 MCU in order to illustrate different architectures＇ effects on chips＇ performance. At last, the factors which affect the performance of SoC, including chip architecture, memory speed, process and frequency, are analyzed and summarized.

关 键 词：芯片架构 片上系统 Cortex—M3 CoreMark 

分 类 号：TN403[电子电信—微电子学与固体电子学]