网络处理器信道解码协处理部件算法级低功耗技术研究  

Algorithm-Level Low-Power Technology for the Channel Decoding Coprocessor of the Network Processor

作　　者：宋丽华[1,2] 郭艳飞[2] 王沁[2] 

机构地区：[1]北方工业大学信息工程学院,北京100144 [2]北京科技大学信息工程学院,北京100083

出　　处：《计算机研究与发展》2012年第8期1641-1648,共8页Journal of Computer Research and Development

基　　金：国家"八六三"高技术研究发展计划基金项目(2008AA01Z134);国家"十一五"科技支撑计划重点基金项目(2009BAI71B02);北京市属高等学校人才强教计划资助项目(PHR201007121);2011年度市教委科研计划资助面上项目(KM201110009002)

摘　　要：以网络处理器的RS(reed-solomon)信道解码协处理部件为研究对象,对传统的信道解码算法进行了低功耗改进并提出了新的LP-RSA算法.通过提前检测误码数的分布情况,该算法能够以尽快、尽少的运算完成求解.基于LP-RSA的解码协处理电路,可根据误码数的检测结果,控制不必要参与运算的电路模块进入休眠状态,节约大量电路翻转带来的功耗浪费.在相同实验条件下,基于LP-RSA的解码协处理部件较传统部件可获得约66.1%的低功耗收益.此外,其研究结果有助于网络处理器在低功耗通信领域的进一步推广和应用.In this paper, a new low power reed-solomon decoding algorithm （LP-RSA） is proposed, with the scenario that the RS decoder is integrated as a coprocessor of network processor. The proposed LP-RSA could dynamically judge the number of error symbols in advance and then close the unnecessary polynomial operations as soon as possible. By inserting the dynamic error pre-judgment circuit, the implemented coprocessor of RS decoder, which complies with the proposed LP-RSA, could turn the unnecessary processing circuits into sleep status to prevent the unavailable toggling of them and reduce the power of the coprocessor of RS decoder as well as the power of network processor. Under the same testing environment, the proposed LP-RSA allows the RS coprocessor achieving about 66.1% gain in power saving. At the same time, the proposed algorithm will help to extend the application range of network processor in the communication system with low power characteristic.

关 键 词：低功耗 RS解码算法 协处理器 网络处理器 DVB-C 

分 类 号：TN47[电子电信—微电子学与固体电子学] TP302[自动化与计算机技术—计算机系统结构]