Class-AB型低功耗轨到轨CMOS模拟缓冲器设计  

A Low-Power Class-AB Rail-to-Rail CMOS Analog Buffer

作　　者：曹桂平[1,2] 宋克柱[1,2] 杨俊峰[1,2] 王砚方[1,2] 

机构地区：[1]中国科学院核探测技术与核电子学重点实验室,合肥230026 [2]中国科学技术大学近代物理系快电子实验室,合肥230026

出　　处：《微电子学》2012年第4期477-480,共4页Microelectronics

摘　　要：设计了一种新型Class-AB轨到轨CMOS单位增益模拟缓冲器。实现电路基于并行互补差分对输入,在保持整个电路简洁的同时,可提供低功耗Class-AB输出方式,使电路实现轨到轨的电平跟踪功能。使用0.35μm工艺库仿真,结果表明,该缓冲器具备较大的电容驱动能力,可以应用在具有大电容负载的场合。使用特殊设计方式,使电路主极点移动到输出节点上,彻底解决了大负载电容下电路的稳定性问题。电路使用3.3V单极性电源,在负载电阻大于1MΩ时,可以提供完全的轨到轨输出。在20pF负载电容时,输出摆率为+7.9V/μs和-5.8V/μs,整个电路的静态功耗仅为184μW。A novel Class-AB rail-to-rail CMOS analog buffer was designed. Based on an input stage consisting of two complementary differential pairs, the proposed circuit could provide low power Class AB output to achieve rail- to-rail level tracking, while maintaining its simplicity. Results from simulation based on 0. 35μm CMOS process library showed that the buffer had high driving capability, suitable for large capacitive load applications. Operating at single 3.3 V supply, the circuit could provide a full range rail-to-rail output for load resistance above 1 MΩ, and it achieved a slew rate of ＋ 7.9 V/μs and -5.8 V/μs for 20 pF capacitive load. The circuit had a quiescent power of only 184 μW.

关 键 词：Class-AB输出 轨到轨 CMOS模拟缓冲器 低功耗 

分 类 号：TN722.7[电子电信—电路与系统]