基于FPGA的全帧紫外CCD驱动时序设计  

Design of driving timing for full-frame UV-CCD based on FPGA

作　　者：胡社教[1] 余升[1] 张铮[1] 

机构地区：[1]合肥工业大学计算机与信息学院,安徽合肥230009

出　　处：《合肥工业大学学报（自然科学版）》2012年第8期1030-1034,共5页Journal of Hefei University of Technology：Natural Science

基　　金：合肥工业大学产学研校企合作资助项目(104-432608)

摘　　要：文章介绍了槟松紫外全帧背照式面阵CCD(S7171-0909)的结构和工作特点,分析了该芯片驱动时序要求;采用可编程逻辑器件EP2C8作为硬件平台,在Quartus II 9.1软件环境下,用基于状态机的算法对时序电路进行了描述,设计产生了芯片正常工作所需的时序脉冲信号,并选用EL7202作为CCD驱动器对时钟脉冲进行功率放大。调用第三方软件进行仿真,并给出实际工作输出波形,结果表明,设计的时序电路满足CCD对各驱动信号的要求。The structure and working characteristics of HAMAMATSU＇ s UV back-illuminated full frame area array CCD（S7171-0909） are introduced and its driving timing is investigated. Using Altera＇s programmable logical device EP2C8 as the hardware platform, under Quartus II 9.1 software environment, the timing circuit functions are described through applying the algorithm based on state machine. The timing pulses of chip under normal working conditions are designed and generated, and the EL7202 is selected as CCD driver to amplify the power of clock pulse. The simulation is conducted through the third-party software and the output waveform of actual work is presented. ,The results show that the designed CCD drive circuits meet the drive requirements.

关 键 词：驱动时序 紫外CCD 时序分析 状态机 现场可编程逻辑阵列(FPGA) 

分 类 号：TP212[自动化与计算机技术—检测技术与自动化装置]