基于FPGA的自定义总线MCMB的设计与实现  

The design and realization of MCMB bus based on FPGA

作　　者：张智鹏[1] 刘娟[1] 白斌[1] 

机构地区：[1]西安电子科技大学电子工程学院,陕西西安710071

出　　处：《电子元器件应用》2012年第8期40-43,60,共5页Electronic Component & Device Applications

摘　　要：针对现在对机载数据采集系统中总线技术的要求,采用Altera公司的CycloneⅢ系列FPGA EP3C40F484,在数据采集系统中实现了自定义数据采集总线MCMB的设计。通过Modelsim进行功能仿真,并利用QuartusⅡ自带的仿真软件SignaltapⅡ在FPGA上调试验证总线IP核设计的正确性。In order to meet the requirements of bus technology for data acquisition system,we use the Cyclone III family FPGA EP3C40F484 of Ahera company achieving MCMB bus IP core in the AT91RM9200-based data acquisition system. We mainly introduce the realization of the MCMB bus IP core based on Verilog HDL Language, simulated on the ModelSim Software. At last we use Signahap II to show the design is feasible.

关 键 词：自定义总线MCMB 机载数据采集系统 MODELSIM QuartusⅡ 

分 类 号：TN925.93[电子电信—通信与信息系统]