综合化航电核心处理系统容错设计  

Design of Fault-tolerance of Integrated Avionics Core Processor System

作　　者：王树义[1] 南建国[1] 赵松云[2] 

机构地区：[1]空军工程大学工程学院 [2]中国人民解放军95809部队

出　　处：《计算机测量与控制》2012年第8期2248-2250,共3页Computer Measurement &Control

摘　　要：新一代综合航空电子系统正向开放式、综合化、模块化的方向发展,作为其基础平台的核心处理系统(ICPS)属于机载实时分布式计算机系统,它的设计直接地关系到综合航电系统的性能和成本;它的可靠性要求很高,必须采用容错技术;介绍了综合航电核心处理系统软/硬件结构,重点对综合处理处理系统硬件系统的动态冗余结构与容错处理进行了设计,提出了增加三模—单模冗余单元(TSRU)的方法,通过该方法提高了系统的容错能力;最后对软件系统容错机制进行了研究。A future avionics will be a open software designed, highly integrated, modularized system, running on its platform called In tegrated Core Processor System （ICPS）, which is real time fault--tolerance distributed computing system, its design relates to performance and cost directly of the new generation integrated avionics systems. In order to meet the high reliability requirement, fault tolerance tech- niques are generally used in designing the ICPS. By describing the hardware and software structure of the IPCS system, the emphasis is to presents dynamic redundancy and the fault-- tolerance handle in hardware , then put forward a method to add a triple--single redundancy unit （TSRU） in the hardware framework, this method improves the fault-- tolerance ability of the system. Finally discuss the fault--toler ance management strategies in the software.

关 键 词：综合航电 核心处理系统 实时分布式计算机系统 容错 动态冗余 

分 类 号：TP302.1[自动化与计算机技术—计算机系统结构]