RS-485图像数据并行传输协议的FPGA设计与实现  

FPGA Design and Implementation of RS-485 Image Data Parallel Transport Protocol

作　　者：蒋玉峰[1] 张志明[2] 崔麦会[1] 尹业宏[2] 

机构地区：[1]海军装备研究院,北京102249 [2]华中光电技术研究所武汉光电国家实验室,湖北武汉430073

出　　处：《电视技术》2012年第17期71-72,共2页Video Engineering

摘　　要：为实现大容量图像数据的传输,设计了一种以同步RS-485为标准的总线控制器,在单片FPGA上实现了2路并行的同步数据链路控制(SDLC)协议。该设计采用功能模块分割的控制时序方式,可移植性好。通过某型光电系统的使用,证明了传输图像数据速率可达32 Mbit/s,误码率低,且稳定可靠,为远距离的高速数据传输提供了硬件化的实现方法。In this paper, a synchronous RS--485 based bus controller is presented for high capability image data transmission, 2 parallel SDLC（ Synchronous Data Link Control ） communication protocol is realized by using FPGA. This design features divide time sequence control of individual function modules, so it is easy to transfer for other applications. The practical application in a type of op-electronic system shows that the data rate for image transmission can be up to 32 Mbit/s with low BER and high stability.

关 键 词：SDLC协议 RS--485 现场可编程门阵列 

分 类 号：TN911.73[电子电信—通信与信息系统] TP273[电子电信—信息与通信工程]