一种用于高速QPSK解调的四次方环载波恢复电路  

A Fourth Power Carrier Recovery Circuit for High-rate QPSK Demodulation

作　　者：王志超[1,2] 王平连[3] 

机构地区：[1]中国科学院光电研究院,北京100094 [2]中国科学院研究生院,北京100094 [3]中国科学院空间应用工程与技术中心,北京100094

出　　处：《电讯技术》2012年第8期1312-1316,共5页Telecommunication Engineering

摘　　要：为解决高速QPSK信号全数字解调的技术瓶颈问题,采用模拟方案,研制了一种四次方环载波恢复电路,重点介绍了应用混频器上变频特性的宽带平方电路以及锁相环(PLL)载波提取电路的设计过程。测试结果表明,该载波恢复电路可以完成载频为720MHz、码速率100Mbit/s～1 Gbit/s范围的QPSK信号同步载波恢复,解决了高速信号相干解调中载波同步的关键技术问题。In order to solve the technical bottleneck of all - digital demodulation for high - rate QPSK signal, a fourth power carrier recovery circuit which uses analog scheme is developed. And especially, the design process of broadband square circuit which applies the frequency up - conversion character of mixer and PLL carrier ex- traction circuit is introduced. The test results show that the circuit can complete the carrier synchronization for QPSK signal whose cartier frequency is 720 MHz and bit rate is in 100 Mbit/s - 1 Gbit/s, which resolves the key technical problem of carrier synchronization in the coherent demodulation of high-rate signal.

关 键 词：卫星数据传输 高速QPSK 全数字解调 四次方环 载波恢复 

分 类 号：TN919.3[电子电信—通信与信息系统]