一种低功耗扩展计数型模数变换器设计  

Design of a Low Power Extended Counting ADC

作　　者：陈宏雷[1] 伍冬[1] 沈延钊[1] 许军[1] 

机构地区：[1]清华大学微电子学研究所,北京100084

出　　处：《固体电子学研究与进展》2012年第4期386-391,共6页Research & Progress of SSE

基　　金：国家863计划资助项目(2009AA04Z321)

摘　　要：扩展计数型模数变换器(ADC)结合了ΣΔ调制器高精度和Nyquist速率ADC速度相对较快的优点,因而获得了广泛的重视。设计了一种13bit的扩展计数型ADC,设计中采用了1.5bit量化技术和硬件复用技术,其中,1.5bit量化技术降低了系统对比较器精度的要求,因而可使用动态比较器来降低系统的功耗。硬件复用技术利用了扩展计数型ADC两步变换分时操作的特点,采用同一套模拟器件实现了两个变换过程,既降低了系统功耗,又减小了核心电路的面积。上述设计采用0.18μm CMOS混合信号工艺流片验证,芯片核心部分的面积只有0.06mm2。测试结果表明该ADC的有效位数(ENOB)为10.6bit,在19.5ks/s的转换频率下功耗只有115μW。The extended counting ADC combines the high accuracy of ΣΔ modulator and the relatively high speed of Nyquist rate ADC. In this paper, an extended counting ADC with 1.5 bit quantizer and hardware reuse technique is designed. The 1.5 bit quantizer in ΣΔ modulator releases the accuracy requirement on the comparators. As a result, the dynamic latch comparator can be used to reduce the power consumption. In addition, the 1.5 bit DAC can achieve high linearity. Therefore the accuracy of the ADC is not influenced. The Nyquist rate ADC reuses the hardware of the ΣΔ modulator and the power consumption is further reduced. The ADC is implemented in 0. 18/lm CMOS technology and the silicon area is only 0.06 mm^2. The power consumption is about 115μW at a 19.5 ks/s conversion rate. The ADC achieves an ENOB of 10. 6 bit.

关 键 词：扩展计数型模数变换 ΣΔ调制器 硬件复用 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN76