一种并行数据采集系统实时硬件抽点设计实现  

Design and realization of hardware-point-extraction in high-speed parallel data acquisition system

作　　者：熊韬[1] 黄建国[1] 邱渡裕[1] 

机构地区：[1]电子科技大学自动化工程学院,成都611731

出　　处：《电子测量技术》2012年第7期108-111,共4页Electronic Measurement Technology

摘　　要：对高速数据流进行实时均匀抽点是高速并行采集系统重要研究内容之一。传统的对串行采样数据流,通过对时钟进行分频的抽点方式在现代并行采集系统中会导致错点或非均匀等一系列错误。分析了具体抽点需求,建立了1个高速数据流抽取矩阵模型,包括高速数据流矩阵、通道选择拼合矩阵、筛选循环单元矩阵,基于该矩阵模型,讨论了在FPGA中相应的并行高速数据实时抽取模块的实现方案,在Vertex-5FPGA平台中实现了对四路并行数据中进行1-2-5步进的整数倍抽点。实验证明该方法可以广泛运用于其他高速采集系统中。Real-time extracting sample points from the high speed data flow uniformly is an important part of high-speed parallel sampling system. We analyze the demand of the points extraction, set up a matrix model of high speed points extraction,including the Matrix of high speed data flow, the matrix of channel selection and the matrix of data selection unit. Based on that,we discuss the solution of the module of high-speed parallel point-extraction in real-time in FPGA, and realize the point-extraction of four channel data flow at the 1-2-5 step in a Vertex-5. The result proved the method has broad applications in the high-speed data acquisition.

关 键 词：并行硬件抽点 FPGA 高速数据采集系统 抽取矩阵 

分 类 号：TP2[自动化与计算机技术—检测技术与自动化装置]