基于FPGA的AVS帧内预测的研究与设计  

Research and design of AVS Intra Prediction Based on FPGA

作　　者：单天燕[1] 王树昆 赵春亮[1] 

机构地区：[1]山东建筑大学 [2]山东省智能建筑技术重点实验室

出　　处：《微计算机信息》2012年第9期156-158,238,共4页Control & Automation

摘　　要：本文通过对AVS视频标准中帧内预测算法的研究,提出了一种新的基于FPGA的AVS解码器帧内预测模块的设计方案。文中设计的通用运算单元,提高了硬件资源的可重构性,降低了帧内预测的计算复杂度。设计中采取有效的控制逻辑,对复杂的plane模式进行预处理,提高了预测速度。上述设计已通过RTL级综合及仿真,并在结合AVS参考模型RM52j和ver-ilog语言的DPI接口建立的验证平台上,验证了该模块功能的正确性。According to the intra prediction algorithm of AVS video standard,this paper proposes a new implementation of intra prediction module for AVS Video decoder based on FPGA.It proposes a general processing element which improves the reusability of hardware resources and reduces the computational complexity of intra prediction.In order to improve the processing speed,plane mode precomputation and effective control logic are adopted.The intra prediction decoder has passed RTL level emulation and synthesis and been tested on a software reference model platform based on RM52j.

关 键 词：AVS视频标准 视频解码 帧内预测 现场可编程门阵列 流水线技术 

分 类 号：TN919.81[电子电信—通信与信息系统]