基于无载频脉冲雷达信号的高速数字采样方法与实现  

Method and Implementation of High-speed Digital Sampling Technology Based on Impulse Radar Signal

作　　者：沈绍祥[1,2] 叶盛波[1] 方广有[1] 

机构地区：[1]中国科学院电子学研究所电磁辐射与探测技术重点实验室,北京100190 [2]中国科学院研究生院,北京100049

出　　处：《雷达学报（中英文）》2012年第2期136-142,共7页Journal of Radars

基　　金：国家自然科学基金(40976114);国家863项目(2008AA121702)资助课题

摘　　要：该文针对无载频脉冲雷达信号周期重复性的特点,提出了一种全新的高速数字采样方法和原理。该方法利用FPGA的差分比较器端口构成高速1bit量化器,采用FPGA内部多相位时钟,对1bit数据流进行并行交替数字采样,并缓冲编码,从而获得上吉赫兹的等效数字采样率。通过将多个比较电平下的1bit采样数据进行累积,从而完成高速数字采样过程。在Xilinx的XC2V3000的FPGA中实现了该方法,获得了采样率达1.6GHz的8bit等效高速模数转换器功能。该设计方法不仅能够提高等效采样方式的效率,而且与高速实时采样相比,具有低功耗、低成本的优势,在实际中获得了良好的应用。A High-speed digital sampling technology suitable for periodical impulse radar signal is proposed in this paper. One bit high-speed quantize is constructed by differential comparator in FPGA. Time-interleaved digital sampling and buffer encoding are used to one bit stream based on the internal multi-phase clock of FPGA, to achieve sampling rate higher than 1 GHz. High speed digital sampling is realized by the accumulation of one bit sampling data with different comparison levels. An 8 bit, 1.6 GHz ADC based on the proposed method is realized on XC2V3000 Xilinx＇s FPGA, which is successfully applied in GPR. The proposed method has the advantages of low cost and power consumption as compared with real sampling, and exhibits higher efficiency as compared with equivalent sampling.

关 键 词：现场可编程门阵列 数字采样 1 bit量化器 比较电平 

分 类 号：TN958.4[电子电信—信号与信息处理]