基于路访问轨迹的指令高速缓存低功耗策略  

Low-power consumption strategy for instruction cache based on way-access track

作　　者：冷冰[1] 严晓浪[1] 孟建熠[1] 葛海通[1] 

机构地区：[1]浙江大学超大规模集成电路设计研究所,浙江杭州310027

出　　处：《传感器与微系统》2012年第9期14-17,共4页Transducer and Microsystem Technologies

基　　金：国家自然科学基金资助项目(90707002;60906012)

摘　　要：现代嵌入式处理器中指令高速缓存的功耗十分显著,对此提出一种基于路访问轨迹的组相联指令高速缓存的低功耗策略,利用改进的指令高速缓存和转移目标缓存建立和维护运行时指令高速缓存的路访问轨迹来减少指令高速缓存命中检测及无关路访问。进一步提出了基于跨行访问前驱指针、转移前驱状态、转移前驱指针及转移目标索引的路访问轨迹信息维护策略用以降低信息重建的频度,从而更有效地利用已建立的路访问轨迹信息。实验结果表明:采用优化后的路访问轨迹策略的指令高速缓存的标志存储器访问和数据存储器访问分别降低到传统指令高速缓存的3.60%和27.70%。In modern embedded microprocessor,power consumption caused by instruction cache is significant. A strategy of low power consumption set-associate instruction cache based on way-access track is proposed. Redundant hit checks and accesses of unrelated data array are eliminated by establishing and maintaining wayaccess track record using modified instruction cache and branch target buffer. Moreover,various way-access track record maintaining strategies, which include pointers to inter-line-access progenitor, states of transfer-access progenitor, pointers to transfer-access progenitor and indexes of transfer targets, is proposed to reduce reestablishment of track record, which improve the utilization of these records. Experiments show that compared with traditional instruction cache, way-access track instruction cache achieves a great reduction of accesses of tag and data, which is only 3.60 % and 27.70 % of traditional instruction cache.

关 键 词：路访问轨迹 指令高速缓存 转移目标缓存 低功耗 

分 类 号：TP302.2[自动化与计算机技术—计算机系统结构]