A low power 14 bit 51.2 kS/s double-sampling extended counting ADC with a class-AB OTA  

作　　者：陈宏雷 伍冬 沈延钊 许军 

机构地区：[1]Institute of Microelectronics,Tsinghua University,Beijing 100084,China

出　　处：《Journal of Semiconductors》2012年第9期108-114,共7页半导体学报（英文版）

基　　金：supported by the National High Technology Research and Development Program of China(No.2009AA042321)

摘　　要：A 14 bit 51.2 kS/s extended counting analog to digital converter （EC-ADC） is presented. Two techniques are utilized to reduce its power consumption. First, a double-sampling configuration based on a fully-floating bilin- ear integrator is proposed to reduce the clock frequency. Second, a class-AB operational transconductance amplifier （OTA） is designed to improve the power efficiency. In addition, the chopping technique is used to eliminate the OTA flicker noise effect. The proposed ADC is fabricated in 0.18 μm CMOS technology with a core area of 0.04 mm2. At a 51.2 kS/s conversion rate, it achieves a 94 dB SFDR and an 11.6 bit ENOB, while consuming only 77 μW from a 1.8 V power supply. The figure of merit is only 0.48 p J/step.A 14 bit 51.2 kS/s extended counting analog to digital converter （EC-ADC） is presented. Two techniques are utilized to reduce its power consumption. First, a double-sampling configuration based on a fully-floating bilin- ear integrator is proposed to reduce the clock frequency. Second, a class-AB operational transconductance amplifier （OTA） is designed to improve the power efficiency. In addition, the chopping technique is used to eliminate the OTA flicker noise effect. The proposed ADC is fabricated in 0.18 μm CMOS technology with a core area of 0.04 mm2. At a 51.2 kS/s conversion rate, it achieves a 94 dB SFDR and an 11.6 bit ENOB, while consuming only 77 μW from a 1.8 V power supply. The figure of merit is only 0.48 p J/step.

关 键 词：A/D converter CLASS-AB DOUBLE-SAMPLING low power 

分 类 号：TN792[电子电信—电路与系统]