猝发式直扩系统伪码同步技术的FPGA实现  

Implementation of PN Code Synchronization with FPGA in Burst-mode DSSS System

作　　者：张福洪[1] 朱小辉[1] 吴铭宇[1] 易志强[1] 

机构地区：[1]杭州电子科技大学通信工程学院,浙江杭州310018

出　　处：《杭州电子科技大学学报（自然科学版）》2012年第4期45-48,共4页Journal of Hangzhou Dianzi University：Natural Sciences

基　　金：浙江省教育厅资助项目(Y201018592)

摘　　要：针对短时猝发式直扩系统中大频偏情况下伪码捕获和跟踪问题,该文提出了一种基于扫频、数字匹配滤波器和数字延迟锁定跟踪环的伪码同步方案,并基于FPGA平台进行硬件实现。试验结果表明该方案可以满足系统设计要求。For the question of PN code acquisition and tracking of spread spectrum signals under large fre- quency offset circumstance in short-term burst-mode DSSS system, an algorithm is proposed to achieved PN code synchronization based on sweeping frequency, digital matched filter and DLL. The algorithm is success- fully validated based on FPGA hardware platform. The results show that the scheme can meet the system de- sign which achieves PN code acauisition and tracking of spread spectrum signals.

关 键 词：扫频 多普勒效应 数字匹配滤波器 数字延迟锁定环 

分 类 号：TN92[电子电信—通信与信息系统]