带通采样时钟沿抖动对解调性能的影响分析  

Analysis of Effect of Clock Jitter in Bandpass Sampling on Performance of Receiver

作　　者：张建志 张丽娜[2] 

机构地区：[1]空军驻石家庄地区军事代表室,河北石家庄050081 [2]中国电子科技集团公司第五十四研究所,河北石家庄050081

出　　处：《无线电工程》2012年第10期10-12,共3页Radio Engineering

摘　　要：在中频直接采样系统中,采样时钟的抖动问题是带通采样的一个关键问题。研究了带通采样时钟抖动对系统的影响,介绍了带通采样时钟沿抖动的产生极其直观影响,分析带通采样时钟沿抖动对解调性能的影响,并仿真验证了理论分析的正确性。结合典型的调制编码方式对带通采样时钟沿抖动范围提出了要求,为带通采样的设计及实现提供了依据。In the system with direct bandpass sampling,the clock jitter is a key problem. The effect of clock jitter on the system is studied. How the clock jitter comes into being is introduced and the effect of the bandpass sampling clock jitter on demodulation per- formance is analyzed. The correctness of the method is verified by simulation results. At last, a requirement for digital bandpass sampling clock jitter is put forward combined with typical modulation and coding schemes.

关 键 词：带通采样 数字化中频 时钟抖动 

分 类 号：TN911.7[电子电信—通信与信息系统]