基于FPGA的H.264解码核的实现  

Implementation of H.264 decoding core based on FPGA

作　　者：付永庆[1] 姜灵灵[1] 

机构地区：[1]哈尔滨工程大学信息与通信工程学院,黑龙江哈尔滨150001

出　　处：《应用科技》2012年第3期9-14,共6页Applied Science and Technology

基　　金：国家自然科学基金资助项目(60772025)

摘　　要：对H.264/AVC的视频解码问题进行了研究,给出了H.264解码核的硬件实现方案,对熵解码CAVLC查表方案进行了优化.介绍了句法预测模块、反量化、逆DCT以及帧内预测模块的具体实现结构;并引入流水线、并行处理和状态机处理方法来提高处理速度,实现了解码结构上的优化.本算法在EP2S60F672C5ES FPGA上获得验证,结果表明给出的H.264解码算法是正确的,且有节省硬件资源和较快解码速度的优点.The video decoding problem ofH.264 was studied, and the implementation of hardware design ofH.264 decoder was given. The look-up table scheme of entropy decoding CAVLC was also optimized. In addition, the concrete realization structure of the syntactic module, inverse quantization, inverse DCT and intra prediction module are introduced. The pipeline, parallel processing and state machine processing method were used to improve the processing speed and realize the optimization of decoding structure. The algorithm was tested and verified in EP2S60F672C5ES FPGA. The results show that H.264 decoding algorithm has the advantages of saving hardware resources and quicker decoding speed.

关 键 词：视频编码标准H.264/AVC H.264解码核 FPGA 句法预测 反量化 逆DCT 帧内预测 

分 类 号：TN919.81[电子电信—通信与信息系统]