利用MAX+plusⅡ平台拓展EDA硬件功能  

Using MAX+PlusⅡ Platform Expand EDA Hardware Function

作　　者：谈进[1] 

机构地区：[1]上海第二工业大学电子与电气工程学院,上海201209

出　　处：《上海第二工业大学学报》2012年第3期198-202,共5页Journal of Shanghai Polytechnic University

基　　金：上海市教委重点学科建设项目(No.J51801)

摘　　要：为了方便操作,减少失误动作,有些数字电路仪器装置的设计,尽可能减少了能够由操作者变通的硬件部分。但由于电路已经固定,随之带来的问题是人们只能在设计者框定的范围内操作或实验,使得实验的范围和灵活性大打折扣。针对某些CPLD/FPGA实验仪器设备的类似缺陷,利用MAX+plusII平台的管脚锁定重新定义功能有效地解决了这一问题,并具体展示了这一过程。Some digital circuit instrument device design, in order to facilitate the operation, reduce false action, as far as possible to reduce the parts by the operator of accommodation to hardware. However, because of the fixed circuit, it will bring on the problem that people can only work in designers＇ limit within the scope of the operation, which makes the scope and flexibility of the experiment reduced greatly. For some CPLD/FPGA instrument equipment of similar defects, a pin lock of MAX ＋ pluslI platform is used to redefine the function and solve the problem effectively, and the specific process is showed.

关 键 词：CPLD/FPGA 管脚锁定 重定义 MAX+plusⅡ 

分 类 号：TN02[电子电信—物理电子学] TN791