4GS/s6位低功耗内插模数转换器设计  

Design of 4 Gsample/s 6-bit Low Power Consumption Interpolation ADC

作　　者：谢莉[1] 余胜[1] 肖奔[1] 张艳蕾[1] 

机构地区：[1]湖南人文科技学院物理与信息工程系,湖南娄底417000

出　　处：《湖南人文科技学院学报》2012年第2期75-79,共5页Journal of Hunan University of Humanities,Science and Technology

基　　金：湖南省科技计划项目(2011GK3172);湖南人文科技学院科学研究项目(2010QN15)

摘　　要：提出一种基于0.18μm CMOS工艺的6位最大采样速率为4GS/s的低功耗内插模数转换器的设计方法:模数转换器采用电阻内插与有源内插级联的两级内插方式,使内插因子达到4。这种内插方式减少了内插放大器和内插电阻的数量,降低了电路的功耗。同时为了提高模数转换器的采样速率,在系统结构上使比较电路与解码电路都采用流水线差分低摆幅的工作方式;且在电路技术上在比较器中使用电感技术,提高了比较器的转换速度而并没有增加功耗。仿真结果表明,此模数转换器积分非线性和微分非线性分别小于0.243LSB和0.124LSB,在100MHz的正弦输入信号下,有效比特数达5.02bits,功耗小于220mW。A 6-bit 4GS/s low power consumption interpolation analog-to-digital converter（ADC） is designed in a 0.18μm CMOS technology.Resistance and active interpolation are cascaded in interpolation mode,which makes the interpolation factor up to 4.So it reduces the number of the interpolation resistances and amplifiers,and it lowers the power consumption.Moreover,pipelining and difference low-swing operation are both in the analog and the digital circuitry results in high-speed low power operation.Besides,using inductor in each comparator improves the sampling rate without an increase in power consumption.Simulation results show that the measured static INL and DNL errors of the ADC are 0.243LSB and 0.124LSB respectively,and its measured ENOB with a 100MHz input is 5.02bits and dissipates 220mW power consumption.

关 键 词：内插技术 模数转换器 流水线 电感技术 

分 类 号：TN792[电子电信—电路与系统]