A 7-27 GHz DSCL divide-by-2 frequency divider  

作　　者：郭婷 李智群 李芹 王志功 

机构地区：[1]Institute of RF-&OE-ICs,Southeast University [2]School of Integrated Circuits,Southeast University [3]Engineering Research Center of RF-ICs and RF-Systems,Ministry of Education,Nanjing

出　　处：《Journal of Semiconductors》2012年第10期92-96,共5页半导体学报（英文版）

基　　金：supported by the National Basic Research Program of China(No.2010CB327404);the National Natural Science Foundation of China(No.60901012)

摘　　要：This paper presents the design and analysis of a high speed broadband divide-by-2 frequency divider. The proposed divider is a dynamic source-coupled logic（DSCL） structure formed with two dynamic-loading master-slave D latches,which enables high frequency operation and low power consumption.This divider exhibits a wide locking range from 7-27 GHz and the minimum power consumption is only 1.22 mW from a 1.2 V supply.The input sensitivity is as low as -25.4 dBm across the operating frequency range.This chip occupies 685×430μm^2 area with two on-chip spiral inductors in 90 nm CMOS process.This paper presents the design and analysis of a high speed broadband divide-by-2 frequency divider. The proposed divider is a dynamic source-coupled logic（DSCL） structure formed with two dynamic-loading master-slave D latches,which enables high frequency operation and low power consumption.This divider exhibits a wide locking range from 7-27 GHz and the minimum power consumption is only 1.22 mW from a 1.2 V supply.The input sensitivity is as low as -25.4 dBm across the operating frequency range.This chip occupies 685×430μm^2 area with two on-chip spiral inductors in 90 nm CMOS process.

关 键 词：BROADBAND frequency divider dynamic source-coupled logic dynamic-loading input-sensitivity CMOS 

分 类 号：TN772[电子电信—电路与系统]