并行CRCC及其在可编程逻辑器件上的实现  

A PARALLEL CYCLIC REDUNDANCY CHECK CODER AND ITS IMPLEMENTATION ON A CPLD CHIP

作　　者：钟宇 龚向东[2] 

机构地区：[1]招商银行南昌支行,江西南昌330006 [2]南昌大学计算机系,江西南昌330029

出　　处：《南昌大学学报（理科版）》2000年第2期165-170,共6页Journal of Nanchang University(Natural Science)

摘　　要：介绍一个具有并行处理功能的循环冗余校验编码器 (CRCC)的逻辑设计 ,该并行CRCC的硬件结构采用硬件描述语言 (HDL)描述 ,并用一片大容量可编程逻辑器件 (CPLD)实现。与串行CRCC相比 。This paper introduces a cyclic redundancy check coder (CRCC) with parallel processing.Design of the parallel CRCC is based on text design entry,in which Atera's hardware description language (AHDL) is used.And the CRCC is Implemented with a complex programmable logic device (CPLD) chip from Altera FLEX10K family.Compared to serial CRCC,encoding efficiency of the parallel CRCC can be considerably raised.

关 键 词：可编程逻辑器件 并行CRCC 循环冗余校验编码器 

分 类 号：TN911.22[电子电信—通信与信息系统] TP303[电子电信—信息与通信工程]