基于伪布尔可满足性的纳米CMOS电路单元配置  

Nano-meter CMOS Circuit Cell Assignment Based on Pseudo-Boolean Satisfiability

作　　者：王先建[1] 王伦耀[1] 储著飞[1] 夏银水[1] 

机构地区：[1]宁波大学信息科学与工程学院,宁波315211

出　　处：《电子与信息学报》2012年第10期2508-2513,共6页Journal of Electronics & Information Technology

基　　金：国家自然科学基金重点项目(61131001);教育部博士点基金(20113305110001)资助课题

摘　　要：针对传统布尔可满足性(SAT)法在处理纳米CMOS电路(CMOL)单元配置时,存在合取范式(CNF)表示的约束子句个数过多、中间处理文件过大的问题,该文提出了利用伪布尔可满足性(PBS)来解决CMOL电路的单元配置问题。实验结果显示,相对于传统的SAT法,PBS法在不增加额外的布尔变量集个数的条件下,通过降低编码过程中的约束个数,能有效减少中间处理文件大小,达到提高算法效率和提高处理大电路的能力。With the deficiency of the efficient of the Boolean SATisfiability （SAT） in the nano-meter CMOS circuit （CMOS/nanowire/MOLecular, CMOL） cell assignment resulted from the huge number of clauses and the big intermediate processing file, a novel approach using Pseudo-Boolean Satisfiability （PBS） to solve the CMOL cell assignment is proposed. The experimental results show that the proposed method can reduce the intermediate processing file efficiently by cutting down the number of the constraints without the additional Boolean variables introduced. The reduction of clauses and the intermediate processing file makes the proposed method work efficiently and improve the ability to deal with bigger circuits in contrast to the traditional SAT-based methods.

关 键 词：纳米CMOS电路 单元配置 布尔可满足性 伪布尔可满足性 

分 类 号：TN402[电子电信—微电子学与固体电子学] TP391.72[自动化与计算机技术—计算机应用技术]