5位1.5GHz采样频率的Flash ADC的设计及数字后台校正实现  

Digital Post-Calibration and Design of a 5 bit 1.5GHz Flash ADC

作　　者：杨阳[1] 赵显利[1] 仲顺安[1] 李国峰[1] 

机构地区：[1]北京理工大学信息与电子学院,北京100081

出　　处：《北京理工大学学报》2012年第9期932-936,共5页Transactions of Beijing Institute of Technology

基　　金：国家自然科学基金资助项目(60976025)

摘　　要：基于TSMC 0.18μm工艺设计了一个单通道5位,1.5GHz Flash模数转换器(ADC),该ADC通过改进跟踪保持电路和采用动态比较器结构实现了数据的高速转换.仿真结果表明,当输入信号达到奈奎斯特频率时,信号与噪声加谐波失真比(SNDR)为24.04dB,无杂散动态范围(SFDR)为29.97dB.为进一步提高此ADC的性能,消除非线性,基于Volterra级数搭建了数字后台校正模型.对比仿真结果,校正后谐波明显下降,SNDR提高了4.91dB,SFDR提高了6.94dB,有效位数提高了约0.82位.This paper presents a designed 1.5 GHz 5 bit flash ADC,in which an optimized track-and-hold circuit and dynamic comparator are adopted to enable high operating frequency of the flash ADC.Simulation results show,the SNDR of the presented ADC is 24.04 dB and the spurious-noise-free dynamic range（SFDR） is 29.97 dB when input signal is at the Nyquist frequency.To improve the performance of the ADC,a digital post calibration model was established based on Volterra series.The comparison results indicate that,with the role of calibration,the harmonics of ADC output have decreased,the SNDR and the SFDR is increased by 4.91 dB and 6.94 dB respectively,which means the effective number of bits（ENOB） is increased by 0.82 bit.

关 键 词：Flash模数转换器 高速转换 VOLTERRA级数 数字后台校正平台 

分 类 号：TN453[电子电信—微电子学与固体电子学]