基于Handel-C的软硬件协同验证方法  

A method of hardware and software co-verification based on Handel-C

作　　者：刘舜奎[1] 蔡艺军[1] 

机构地区：[1]厦门大学电子工程系,福建厦门361005

出　　处：《电子技术应用》2012年第10期52-55,共4页Application of Electronic Technique

摘　　要：针对数字集成电路中传统IP验证方法效率不高的问题,提出了一种新的IP验证方法。该方法以OpenGL-ES中坐标变换算法为例,利用Handel-C对其进行建模并用FPGA实现。最后与软件测试平台进行了协同验证。验证结果表明,对复杂的验证模块而言,该方法和传统的Modelsim仿真对比,在速度上具有明显的优势。Aiming at the low efficiency of the traditional IP verification method in digital circuit design, a new IP verification method is proposed. This method takes the coordinate transformation algorithm in OpenGL-ES for example. It uses Handel-C to model the algorithm, and FPGA to implement this algorithm rapidly. The FPGA platform works with the software platform at last. The result shows that when the scale of the design under test is large, the method has obvious advantages in speed than the tradi- tional Modclsim simulation.

关 键 词：3D FPGA Handel—C DMA 协同验证 

分 类 号：TN47[电子电信—微电子学与固体电子学]