FPGA implementation of bit-stream neuron and perceptron based on sigma delta modulation  

基于总和增量调制的比特流人工神经元和感知器的FPGA实现(英文)

作　　者：梁勇[1] 王志功[1] 孟桥[1] 郭晓丹[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《Journal of Southeast University(English Edition)》2012年第3期282-286,共5页东南大学学报（英文版）

基　　金：The National Natural Science Foundation of China (No.60576028);the Natural Science Foundation of Higher Education Institutions of Jiangsu Province(No.11KJB510004)

摘　　要：To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural network（ANN） hardware implementation methods,a bit-stream ANN hardware implementation method based on sigma delta（ΣΔ） modulation is presented.The bit-stream adder,multiplier,threshold function unit and fully digital ΣΔ modulator are implemented in a field programmable gate array（FPGA）,and these bit-stream arithmetical units are employed to build the bit-stream artificial neuron.The function of the bit-stream artificial neuron is verified through the realization of the logic function and a linear classifier.The bit-stream perceptron based on the bit-stream artificial neuron with the pre-processed structure is proved to have the ability of nonlinear classification.The FPGA resource utilization of the bit-stream artificial neuron shows that the bit-stream ANN hardware implementation method can significantly reduce the demand of the ANN hardware resources.为了解决传统的多比特数字方法在实现人工神经网络时所存在的硬件规模过于庞大的问题,提出了一种基于总和增量(ΣΔ)调制的比特流人工神经网络硬件实现方法.在FPGA中实现了比特流加法器、乘法器、阈值函数单元和全数字ΣΔ调制器,并采用这些比特流运算单元构建了比特流人工神经元.用实现逻辑函数功能和线性分类器的方法验证了比特流人工神经元的功能.基于比特流人工神经元的带预处理结构的比特流感知器被证明具有非线性分类的能力.比特流人工神经元实现所使用的FPGA资源表明比特流人工神经网络硬件实现技术可以显著地减少人工神经网络对硬件资源的需求.

关 键 词：bit-stream artificial neuron PERCEPTRON sigma delta field programmable gate array（FPGA） 

分 类 号：TN710[电子电信—电路与系统]