基于FPGA的Σ-Δ ADC数字抽取滤波器Sinc^3设计  

Design of Sinc^3 Decimation Filter for Σ-Δ A/D Converter Based on FPGA

作　　者：王霄航[1] 

机构地区：[1]华中科技大学电子信息工程系,武汉430074

出　　处：《微电子学》2012年第5期655-658,共4页Microelectronics

摘　　要：针对Σ-ΔADC输出端存在的高频噪声问题,设计了一种Sinc3数字抽取滤波器,实现了Σ-Δ调制器输出信号的高频滤波。分析了Sinc3滤波器的结构原理,基于Spartan-6FPGA进行滤波器的设计与实现,并进行了实验验证。实验结果表明,该数字抽取滤波器不仅结构简单,无需实现乘法运算,便于硬件实现,且能有效滤除高频噪声,具有较强的实用性。A Sinc3 decimation filter was designed to filter out high frequency noise signal of the Σ-Δ modulator.Construction of the Sinc3 filter was analyzed,and a Sinc3 filter was designed and implemented based on Spartan-6 FPGA.Simulation results indicated that the decimation filter,which requires no multiply-operation and so was easy for hardware implementation,could filter out high frequency noise effectively.

关 键 词：A/D转换器 数字抽取滤波器 现场可编程门阵列 

分 类 号：TN76[电子电信—电路与系统]