基于氧化铟锡的无结低电压薄膜晶体管  

Junctionless low-voltage thin-film transistors based on indium-tin-oxide

作　　者：赵孔胜[1] 轩瑞杰[1] 韩笑[1] 张耕铭[1] 

机构地区：[1]湖南大学微纳光电子器件教育部重点实验室,长沙410082

出　　处：《物理学报》2012年第19期425-429,共5页Acta Physica Sinica

基　　金：国家重点基础研究发展计划(973计划)(批准号:2007CB310500);国家自然科学基金(批准号:10874042)资助的课题~~

摘　　要：在室温下制备了基于氧化铟锡(ITO)的底栅结构无结薄膜晶体管.源漏电极和沟道层都是同样的ITO薄膜材料,没有形成传统的源极结和漏极结,因而极大的简化了制备流程,降低了工艺成本.使用具有大电容的双电荷层SiO_2作为栅介质,发现当ITO沟道层的厚度降到约20 nm时,器件的栅极电压可以很好的调控源漏电流.这些无结薄膜晶体管具有良好的器件性能:低工作电压(1.5 V),小亚阈值摆幅(0.13 V/dec)、高迁移率(21.56 cm^2/V·s)和大开关电流比(1.3×10~6).这些器件即使直接在大气环境中放置4个月,器件性能也没有明显恶化:亚阈值摆幅保持为0.13V/dec,迁移率略微下降至18.99 cm^2/V·s,开关电流比依然大于10~6.这种工作电压低、工艺简单、性能稳定的无结低电压薄膜晶体管非常有希望应用于低能耗便携式电子产品以及新型传感器领域.Bottom-gate junctionless thin-film transistors （TFFs） based on indium-tin-oxide （ITO） are fabricated at room temperature. Source/drain electrodes and channel layer are the same ITO thin films without source/drain junction formation, hence the fabrication process is greatly simplified and the fabrication cost is reduced. We employ electric-double-layer （EDL） Sit2 with large capacitance as the gate dielectric, and find that the drain current can be effectively modulated by the gate bias when the thickness of ITO film decreases to about 20 nm. These junctionless TFTs show excellent electrical performances with a small subthreshold swing of 0.13 V/dec, a high mobility of 21.56 cm2/V.s and a large on/off ratio of 1.3 × 106. The performances of these junctionless TFTs do not show significant degradation even after 4 months in air ambient, the subthreshold swing is still 0.13 V/dec, the mobility slightly decreases to 18.99 cm2/V-s and the on/off ratio is still larger than 106. Such TFTs are very promising for the applications in low-cost low-power portable electronic products and novel sensors.

关 键 词：薄膜晶体管 无结 低电压 氧化铟锡 

分 类 号：TN321.5[电子电信—物理电子学]