延迟约束下的功耗与热感知NoC映射  

Power-and thermal-aware mapping for NoC under latency constraint

作　　者：董文箫[1,2] 沈海斌[1] 全励[1] 严晓浪[1] 

机构地区：[1]浙江大学超大规模集成电路设计研究所,浙江杭州310027 [2]海思半导体有限公司,上海201206

出　　处：《电路与系统学报》2012年第5期19-25,共7页Journal of Circuits and Systems

基　　金：国家自然科学基金资助项目(60720106003)

摘　　要：随着片上网络(NoC)集成度的提高,功耗逐渐成为设计的焦点。此外,由于工艺尺寸的进一步缩小,芯片的功耗密度逐渐增加,使得芯片温度急剧上升。本文考虑了链路功耗和静态功耗,提出了一种延迟约束下的针对功耗和温度的NoC多目标映射方法。该方法基于遗传算法,使用数组方式编码染色体,并采用非常规的交叉和变异运算因子。实验结果表明,本文的多目标算法与单目标遗传算法相比,在只增加0.3%功耗的情况下能降低3.9%芯片峰值温度。As the number of components in Network-on- Chip （NoC） increases, power becomes a critical issue. Moreover, the scaling of MOS transistors increases the power density, which causes the temperature in high performance chip to rise dramatically. To deal with these, a power-and thermal-aware NoC mapping approach under latency constraint is proposed,which takes link power and static power into consideration. This approach is based on genetic algorithm, which encodes the chromosome as an array of integers, and uses irregular crossover and mutation operations. The results show that the proposed approach could reduce the peak temperature of chip by 3.9% than SGA, but only increase 0.3% in power consumption.

关 键 词：片上网络 功耗 热 延迟约束 映射 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]