一种结构简单的低压、低功耗CMOS 4象限模拟乘法器设计  

Design of a Compact Low-voltage,Low-cost CMOS Four-quadrant Analogue Multiplier

作　　者：张桂英[1] 戴宇杰[1] 张小兴[1] 吕英杰[1] 

机构地区：[1]南开大学微电子学研究所,天津300457

出　　处：《南开大学学报（自然科学版）》2012年第4期63-66,共4页Acta Scientiarum Naturalium Universitatis Nankaiensis

基　　金：天津市科技支撑计划国际科技合作项目(09ZCGHHZ00200)

摘　　要：提出了一种结构简单的低压、低功耗CMOS 4象限模拟乘法器,详细分析了电路的结构和设计原理.乘法器基于交叉耦合平方电路结构,并采用减法电路来实现.整个乘法器电路由8个MOS晶体管和2个电阻组成.基于SMIC 0.18μm CMOS工艺,采用Cadence Spectre软件对电路进行了仿真验证.仿真结果表明,在1.2 V单电源电压下,其输入电压线性范围约为±0.2 V,-3 dB带宽约为4.8 GHz,电路静态功耗低至25μW.A compact low-voltage, low-cost CMOS four-quadrant analog multiplier was presented and its basic configuration and design principle were analyzed. The proposed multiplier was designed based on a cross-coupled squarer topology and implemented with subtraction circuits. It consists of eight MOS transistors and two resistances. The circuit was simulated with Cadence Spectre based on Chartered 0.18 μm CMOS technology. The results indicate that the full-scale linear input range is ± 0.2 V and the simulated - 3 dB bandwidth is about 3 GHz for 1.2 V single power supply. The pow- er consumption of this analog multiplier is less than 25 μW.

关 键 词：模拟乘法器 低电压 低功耗 

分 类 号：TN43[电子电信—微电子学与固体电子学]