一种基于低成本FPGA的高速8B/10B编解码器设计  

A High Speed 8B/10B Encoder/Decoder Design Based on Low Cost FPGA

作　　者：陈章进[1,2] 钟国海[1,2] 毕卓[1,2] 

机构地区：[1]上海大学计算中心 [2]上海大学微电子研究与开发中心,上海市200072

出　　处：《微计算机信息》2012年第10期189-190,480,共3页Control & Automation

基　　金：上海科学技术部项目(No.09530708600和No.09ZR1412000);上海市国际科技合作基金项(No.09700714000)的资助

摘　　要：本文基于Altera低成本FPGA设计并实现了一种高速8B/10B编码解码器,编码器和解码器均采用并行流水线设计,可以作为高速串行总线中的编码器和解码器用于保证直流平衡、提高时钟恢复能力等。在Altera公司软件平台QuartusⅡ上进行的综合和仿真结果表明,将该编解码器应用到基于CycloneⅢ设计的高速SERDES中,可获得超过1.25Gbps的单通道数据率,能够满足高速串行通信要求。In this paper, a high speed 8B/10B Encoder/Decoder is presented in this paper. The Encoder/Decoder is based on Ahera＇ s low cost FPGA Cyclone family. The Encoder/Decoder includes parallel pipeline structure. The Encoder/Decoder is applied to the Serializer/Deserializer （SerDes） of high-speed serial bus. The Encoder/Decoder is synthesized and simulated by Quartus II. The syn- thesis and analysis results show the maximum frequency is more than 359MHz. The timing simulation results show the clock frequen- cy is more than 125 MHz. The single channel data rate of serial bus can get to 1.25Gbps. The proposed Eneoder/Decoder can meet the requirements of most hi^h-speed serial bus.

关 键 词：关键字 8B 10B编码 FPGA SERDES 串行总线 

分 类 号：TP331.2[自动化与计算机技术—计算机系统结构]