一种串行高速芯片互连接口逻辑设计与实现  

Design and Implementation of a Serial High-speed Chip Interconnect Interface Logic

作　　者：李仁刚[1,2] 王恩东[1,2] 胡雷钧[1,2] 秦济龙[2] 

机构地区：[1]高效能服务器和存储技术国家重点实验室,济南250013 [2]浪潮(北京)电子信息产业有限公司,北京100085

出　　处：《科学技术与工程》2012年第31期8235-8240,共6页Science Technology and Engineering

基　　金：核高基专项(2011ZX01034-002-002-004);973计划(2010CB735905);高效能服务器和存储技术国家重点实验室课题基金资助

摘　　要：在计算机系统中,总线技术对整个系统的性能和功能都有直接影响,通过研究高速信号传输的特点,分析串行高速芯片互连协议,实现了一种串行高速芯片互连接口逻辑,并实现了FPGA平台的与处理器互连和芯片间互连的验证。最终达到了设计性能要求和可靠性要求,互连接口数据传输速率达到6.4GT/s。Bus technology has a direct impact on the performance and functionality of computer system. By study the characteristics of high-speed signal transmission, analysis the specification of serial high-speed chip inter- connection, a logic of serial high-speed chip interconnect interface is implemented, and verified with FPGA plat- form in processor interconnect and chip interconnect. Eventually the design meets the requirements of the perform- ance and reliability, and the data transfer rates of interface is 6. 4 GT/s.

关 键 词：串行总线接口 扰码 FPGA 可靠性 

分 类 号：TN407[电子电信—微电子学与固体电子学]